Hi,everyone
I’m also working on the AD-FMCOMMS3 with the ML605,and I have seen the provided cf_ad9361_ml605 xps project and using the No-OS softwareto control the AD9361 part in ISE 14.6. No that we have successfully initialized the
AD-FMCOMMS3,and we have seen the sine wave,we now want to use our own transmit data in ISE,only using the no-os software to initialize the ad9361,but I met some problems.
You have make external the following pins in the XPS:
PORT rx_clk_in_p = "", DIR = I, SIGIS = CLK
PORT rx_clk_in_n = "", DIR = I, SIGIS = CLK
PORT rx_frame_in_p = "", DIR = I
PORT rx_frame_in_n = "", DIR = I
PORT rx_data_in_p = "", DIR = I, VEC = [5:0]
PORT rx_data_in_n = "", DIR = I, VEC = [5:0]
PORT tx_clk_out_p = "", DIR = O
PORT tx_clk_out_n = "", DIR = O
PORT tx_frame_out_p = "", DIR = O
PORT tx_frame_out_n = "", DIR = O
PORT tx_data_out_p = "", DIR = O, VEC = [5:0]
PORT tx_data_out_n = "", DIR = O, VEC = [5:0]
But I want to make external the sample clk(I mean the 30.72Mhz clk) and the 12-bit data rx_data_i1 , rx_data_i2 , rx_data_q1 ,rx_data_q2 for receive and
tx_data_i1,tx_data_i2,tx_data_q1,tx_data_q2. So, I changed the provided HDL file in ...\cf_ad9361_ml605\pcores\axi_ad9361_v1_00_a\hdl\verilog
What I changed in the HDL files is only add the ports above to the axi_ad9361.v .Then I should re-import the modified file into my XPS project,I did it as following in the XPS:
- I open the CIP wizard and import the exist peripheral
I select the current project on the repository or project page and name it axi_ad9361 1.01a
2.I select the current project on the repository or project page and name it axi_ad9361 1.01a
3.I choose the source type :
4.I use the .mpd and .pao file .
5.I select the BUS INTERFACE as followed:
6.I set the parameter : To make the parameters the same as the origin ,I made the following changes :
7.After finish the CIP wizard,I add this IP core to the XPS project and delete the origin, I set the exact same parameters as the origin and the same connections,(except for the added port ,I make them external). I also change the UCF files .
8.Then I import the new XPS project to a ISE project and make some errors during the translate :
ERROR:NgdBuild:604 - logical block
'system_i/axi_ad9361_0/axi_ad9361_0/i_dev_if/i_rx_frame_idelay' with type
'IDELAYE2' could not be resolved. A pin name misspelling can cause this, a
missing edif or ngc file, case mismatch between the block name and the edif
or ngc file name, or the misspelling of a type name. Symbol 'IDELAYE2' is not
supported in target 'virtex6'.
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I have tried the solution provided by xilinx but it didn’t work
WHY? Is it because of some missing ngc files that you didn’t provide.?
Can you tell me how to modify the HDL files and make a new IP according to the provided axi_ad9361 IP core?
Or can you give me some advices if I want to use the 12- bit transmit/receive data instead of the so-call Device Interface :rx_clk_in_p/n etc.?
WISH YOUR REPLY SOON! DragosB fkgong
yours,
wang zhi