Hi Guenter,
I would like to add some more explanations to this issue:
2) No, it is not reflection. The 'glitch' can be moved by altering the phase delay of the ADV7842 outputs. Hence it is not clock signal reflection.
4) No. Attaching a probe just adds capacity to the line and hence it can smoothen the glitch slightly which then causes the FPGA input to miss it. This will probably not be valid for all boards / parts.
A few important things to notice with the 'glitch':
a) It is always present near or on the rising edge of the clock.
b) Data output edge is indifferent, on the plots data are shifted on falling edge of LLC.
c) The 'glitch' follows DLL mux and phase delay settings and is hence not (directly) a signal integrity issue. It can be a power related issue, but then it needs to be something internally in the ADV7842 that switches a lot of signals on the rising edge of LLC, and always on the rising edge.
Regards
Håvar