Re: AD9361 VDD_INTERFACE
Digital interface levels are specified in the datasheet. Please look in the specification tables. GPO run from a different supply, not VDD interface. The supply is VDDA_GPO and its maximum level is 3.3V.
View ArticleRe: AD9361 RX_FRAME and TX_FRAME signals in FDD
ENABLE and TXNRX are sampled by FB_CLK. Are you stopping FB_CLK?
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Re: ADIsimPE How do I check the number of node
TM, there is no function in ADIsimPE or SIMETRIX/SIMPLIS to count nodes or components on the schematics. The limitations on ADIsimPE are not fixed, they depend on the needed schematics necessary for...
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DSP chip with the smallest package
Could anybody tell me the DSP chip with smallest package? BGA package is not allowed in our project. Thank you.
View ArticleRe: ADM7170, ADM7171, ADM7172 soft start
Luca, The SS pin was never intended to work this way so we'd have to test it in the lab to see what happens. Here's a brief explanation of how the SS pin works... The SS cap does not bypass the...
View ArticleRe: ADF4351 PLL programming question
Yes, they said they provide support only for using complete USRP software defined radio kit. I am only using their transceiver. That board has 2 PLLs and both show same error so I think I am missing...
View ArticleRe: AD9625 Noise Figure and IIP3 values and calculations?
After looking through some of my research on this topic some more, I recall another method of calculating the ADC dBm input level at 0dBFS. The formula is generically "Full Scale Signal Power Level...
View ArticleRe: ADF4351 PLL programming question
Can you check the voltage level on the CE and PDBrf pins? Both pins should be logic high. If that doesn't work, use the USRP software to monitor the SPI signals. Note what register values are being...
View ArticleRe: Post LPF Gain Stage
Hi Kris, To simplify things, I decided to have a bit of gain in the filter stage - about 3dB. This also provided a Vdd/2 bias circuit (using AD8031) which should be a low enough impedance path for the...
View ArticleAbout the ADXL362's activity detection feature.
How does the "reference" mode in the ADXL362 activity detection work?
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Filter Network Phase / Gain Margin
Hi, Part of the design files from the Filter Wizard included the "ACanalysis.cir" file which I'm able to run in SPICE. Here is what appears to be a reasonable definition of phase margin (from...
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Re: About the ADXL362's activity detection feature.
In reference mode, the operation of the ADXL362 should be thought of this way. Here’s an example: Let’s say you enable the activity interrupt (set threshold = 0.5g, samples number = 2, use AC mode or...
View ArticleRe: AD7879 device tree node.
Ok. I kind of solved that problem after reading another thread on this board related to AD7879 and changing trigger edge from falling to rising in a driver. Now I'm successfully pass device...
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Error with ADXL345 Pmod Reference Design with ZedBoard
Hello all, I am new to FPGAs. I am attempting to implement the ADXL345 Pmod Reference Design on the ZedBoard from ADXL345 Pmod Xilinx FPGA Reference Design [Analog Devices Wiki] After correcting the...
View ArticleRe: Is AD8302 a lock-in amplifier?
Hi Andy, The AD8302 is not a lock-in amp, or at the very least, it is best not to think of it as such. The phase detector is an XOR style that basically detects the zero crossings of the limited...
View ArticleRe: Increasing phase measurement accuracy around 0/180/-180 degrees for AD8302
Hi Andy, Here's the answers to your questions: 1) You cannot fundamentally increase the accuracy at 0, 180 and -180 degrees of phase. The accuracy is what the accuracy is, and is inherent in the XOR...
View ArticleRe: Pin Muxing in CCES 1.1.0 for ADSP-BF538F
Hi Anand, The peripherals mapped to Port F (SPI0, PPI and Timers) don't use the Pin Muxing Add-in because Port F doesn't have a Function Enable register (FER). The peripherals on Port F are enabled...
View ArticleTX port baluns and impedances
Hi tlili I'm designing for an application that covers about 200MHz to 3GHz. My application has a very limited maximum component height of 2mm (80mils). From all the part searches I've done this...
View ArticleRe: Setting LO frequency taking 40-60ms with libiio
When will the driver fix show up in the Xilinx boot image? I'd like to be able to just use the adi_update_boot.sh script to get the driver fix. Thanks, Tom
View ArticleRe: Re: Filter Network Phase / Gain Margin
Hi, Thanks to all for responding. I should mention that the ".cir" file from the Filter Wizard is OK, no issues there (as mentioned).The question is...when I create the circuit in Spice, using ADI's...
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