Yes. ADP7182 can be used as current source.
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Re: LDO as current source
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Re: Setting up a Custom Profile for LTE20MHz using IIO Oscilloscope in AD9371
Hi Rejeesh,
I tried to update JESD, XCVR IP cores and IP cores and compiled a rbf file.
I also generated a uboot_w_dtb-mkpimage.bin based on instructions on Altera SOC Quick Start Guide [Analog Devices Wiki]
I also updated ad9371.c with the setting based on the matlab filter wizard. For devicetree, I have modifed dts file (see attached file) and then using dtc script back to dtb and I am seeing the following error:
root@analog:~# [ 131.991600] altera_xcvr ff220000.xcvr_core: RX transceiver NOT ready [00fc]
[ 133.539006] altera_xcvr ff240000.axi_os_jesd_xcvr: RX transceiver NOT ready [00ff]
[ 136.541599] altera_xcvr ff220000.xcvr_core: RX transceiver NOT ready [00fc]
[ 138.089041] altera_xcvr ff240000.axi_os_jesd_xcvr: RX transceiver NOT ready [00ff]
[ 141.091603] altera_xcvr ff220000.xcvr_core: RX transceiver NOT ready [00ff]
[ 142.639022] altera_xcvr ff240000.axi_os_jesd_xcvr: RX transceiver NOT ready [00ff]
Can you help take a look at the settings?
Regards,
Benson
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ADUM5000W PSPICE Library
Could I have ADUM5000W PSPICE library?
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PLL Design Tool
Hi,
I have a problem with PLL design software. Instalation is succesful, but problem is with MCR.
I have Matlab 2011, so i try instal new version 2015, problem still alive (picture PLL1.png)
I found in forum on EngineerZone at https://ez.analog.com/welcome installer: MCRInstaller7p11.exe If I install it, there is no error message. After turn on PLL Design there is only picture (PLL2.png) and after program is turn off.
Thanks for your help,
Martin Uhlík
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AD9361 DUAL PORT FULL DUPLEX MODE (CMOS)
I'd like to setup SW to use AD9361 DUAL PORT FULL DUPLEX MODE (CMOS). How to setup AD9361_InitParam default_init_param?
I captured the default setup from eval software.
1, //lvds_mode_enable *** adi,lvds-mode-enable
0, //half_duplex_mode_enable *** adi,half-duplex-mode-enable
0, //single_port_mode_enable *** adi,single-port-mode-enable
0, //full_port_enable *** adi,full-port-enable
0, //full_duplex_swap_bits_enable *** adi,full-duplex-swap-bits-enable
Thanks
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ADL5315 Voltage measure and current control
I have a question about ADL5315.
I'm looking at the voltage to current converting (BIAS CONTROL INTERFACE, Datasheet Page 10)
I will measure the sensor voltage and control the current.
If measured sensor voltage is higher than VSET, control the current to be lower.
If measured sensor voltage is lower than VSET, control the current to be higher.
Question :
1. Can it be possible to control the Iout current by measuring sensor voltage?
2. How to expect IOUT current with regard to VSET?
3. Could I connect IOUT to the load to supply current?
4. In this condition, How to connect SREF pin?
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Re: AD7124-4 Noise Performance
Hi,
1. It is necessary to apply a bias voltage so that the inputs are at a certain fixed voltage level to ensure that the common mode voltage level of the signal is within the acceptable input range.
2. Biasing at mid supply is an appropriate voltage level for noise test as amplifiers tends to perform better when their outputs are far away from the rails. Thus, AD7124 noise specifications are also tested with internal VBIAS enabled.
3. There's nothing much difference as long as both inputs are tied together, you can enable the biased voltage on either or both of the inputs.
Thanks,
Jellenie
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Re: PWM Delay when updating duty cycle
Ok I will do that,
Thank you for your answer,
Jeremy
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EVAL-ADV739x Register Control Problem
Hi,
I use the ATV Benchtop software to control the EVAL-ADV739x board, AD7403_xc3s400_adv7391-VER.1.2.c. I choose the setting of ##SD## : AUTODETECT NTSC/PAL/SECAM 10-Bit 422 out through encoder. I found some of the value of register is not as same as it in the **.txt. And some of the registers have two same address but different value.
In the **.txt the value of address 52 is 0x46, but it shows 0xC8. There are two address 98, address 99 .... One is read only, another is write only. I write a new value to the write only one, and then read the read only one, the value is not the value which is I write. So why ?
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FMCDAQ2 lanes configuration
why are these lanes crossed like that? do I need to keep them that way? when connecting additional channels do I need to follow this convention? thanks!
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Re: If i use a AVdd of 5V and buffer on(ADuC7122) or external reference (ADuC7023) , then can i use signals with 5V input to ADC pins as well as output of 5V from DAC pins.
The ADuC7x2x products are rated to survive the max. rating and GPIOs can be used with external pull-up's to work on 5V I/Os. But the parts are only qualified/specified to work in a range of 2.7V to 3.6V. Outside this range the detailed parameters are not guaranteed.
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Re: FMCDAQ2 lanes configuration
I've branched this into a new thread because the first questions from the old one were already answered and these new ones are somehow not related to them.
Dragos
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Re: Install Libiio to Petalinux OS
You can continue to use the rootfs of your choice.
However we use the same Ubuntu image for all our reference designs, which includes the libiio and a few other tools.
You can download the latest image from here:
https://wiki.analog.com/resources/tools-software/linux-software/embedded_arm_images
It also includes support for AD9371/ZC706.
-Michael
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Re: AD9361 output power
Thanks
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AD7924 SPI error
Hi guys.
I bought a little AD7924.
I tried to use it, but it did not work well.
Several experiments have shown that the CSB and DIN (MOSI) of the SPI interface are reversed from the datasheet.
I would like to know if the AD7924 I purchased is faked or defective.
The chip is marked as follows.
7924
BRUZ
# 551
Please answer.
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Re: ADUC7061 differential reference
As specified in the datasheet the recommended input range for all analog inputs is 0.1V to AVDD with max. ratings given from -0.3 V to AVDD + 0.3 V.
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Re: J-Link LITE won't connect to ADSP-CM408F EZ-KIT Lite
I've installed the ADSP-CM40x Enablement Package (Rev. 2.1.0) but still have ' Bad JTAG communication'.error on the ADSP-CM408F EZ-KIT.
.
Here it is,
Logging started @ 2016-12-22 07:18
DLL Compiled: May 5 2015 11:00:52
Firmware: J-Link ARM Lite V8 compiled Oct 29 2014 09:03:16
Hardware: V8.00
S/N: 228209829
Feature(s): GDB returns O.K. (0272ms, 0272ms total)
T1184 000:272 JLINK_ExecCommand("ProjectFile = D:\exp2\settings\exp2_Debug.jlink", ...) returns 0x00 (0000ms, 0272ms total)
T1184 000:272 JLINK_ExecCommand("scriptfile = C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\AnalogDevices\CM40z.JLinkScript", ...) returns 0x00 (0000ms, 0272ms total)
T1184 000:272 JLINK_ExecCommand("device = CM40z_384_2048", ...)Device "ADSP-CM407BSWZ-BF" selected. returns 0x00 (0001ms, 0273ms total)
T1184 000:273 JLINK_GetDLLVersion() returns 49805 (0000ms, 0273ms total)
T1184 000:273 JLINK_GetCompileDateTime() (0000ms, 0273ms total)
T1184 000:273 JLINK_GetFirmwareString(...) (0000ms, 0273ms total)
T1184 000:273 JLINK_SelectDeviceFamily(14) (0000ms, 0273ms total)
T1184 000:273 JLINK_SetSpeed(1000) (0002ms, 0275ms total)
T1184 000:275 JLINK_ExecCommand("SetResetType = 3", ...) returns 0x00 (0000ms, 0275ms total)
T1184 000:275 JLINK_ExecCommand("SetResetPulseLen = 200", ...) returns 0x14 (0000ms, 0275ms total)
T1184 000:275 JLINK_SetResetDelay(0) (0000ms, 0275ms total)
T1184 000:275 JLINK_ResetPullsRESET(ON) (0000ms, 0275ms total)
T1184 000:275 JLINK_Reset()******************************* J-Link script: Init CM408x ******************************* >0x2B0 JTAG>TotalIRLen = 5, IRPrint = 0x01 >0x30 JTAG> >0x210 JTAG>CM408x (InitTarget): Enabling access to CPU core via TAPC >0x0A JTAG> >0x24 JTAG>CM408x (InitTarget): Sending security key needed for CPU core access >0x0A JTAG> >0x03 JTAG> >0x20 JTAG> >0x20 JTAG> >0x20 JTAG> >0x21 JTAG> >0x01 JTAG> >0x0A JTAG> >0x0C JTAG> >0x0A JTAG> >0x0E JTAG> >0x25 JTAG> >0x2A8 JTAG>
TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG> >0x70 JTAG>
***** Error: Bad JTAG communication: Write to IR: Expected 0x1, got 0x0 (TAP Command : 10) @ Off 0x5. (0071ms, 0346ms total)
T1184 000:275
***** Error: Error while identifying Cortex-M device. Wrong AHB ID. Expected 0x04770001, found 0x00000000
Closed
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Re: ADT7420 reportable temperature range
Hi,
A code will be output, but its accuracy will degrade considerably. Note the package and lead frame on ADT7420 is different that the used on ADT7310, so this part is not specified to down to that temperature.
Is your application working down to that temperature range (-55C to -40C) normally? What the reason for upgrading, what's your accuracy needs?
Thanks,
Lluis.
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Re: 7612 not detecting a source device
Hi,
Can you please let us know the software driver version that you have been using it?
Please provide the Rs-232 console log file for our analysis.
Best Regards,
Jeyasudha.M
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Re: ADT7420 reportable temperature range
It will theoretically be working down to -50/-55, but it's not going to happen very often. An accuracy of +/-0.25 to 0.5 degrees Celcius below -40 would be nice. I've been unable to find any informaiton on accuracy degradation below -40 on the ADT7420.
This is for a new product. Currently we're going to fit the ADT7410 which has a lower operating range (-55), but we would like the smaller footprint and higher accuracy of the ADT7420.
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