Hi,
Please see my replies below:
“Thus, I believe we must consider Figure 11 and Figure 19 at the same time, for the timing of Synchronous Read/Write as Bus Mater.
Please correct me if I'm wrong.”
>> Yes, both the timings should be taken care by the user. Also please note when interfacing to synchronous external memories, CLKIN must be used to provide the clock source to the synchronous device. CLKOUT with CLKDBL tied low can be used as a clock source to peripherals only in single processor systems.
Even the datasheet on page 31 states that ‘Use these specifications for interfacing to external memory systems that require CLKIN, relative to timing or for accessing a slave ADSP-21161N (in multiprocessor memory space).’
“If it is correct, I would like to ask you following question, a) When defining 1 or 2 wait-state, how this wait-state value affect to RD and WR signal on the timing chart ?
I think WR and RD change on CLKOUT's edge, therefore as far as CLKOUT cycle is NOT changed, WR and RD cycle(means duration time from signal rising to the next rising, or from rising to falling) will not be changed, I think, but is this correct ?”
>> Kindly refer to page 475, of the Hardware Reference manual which explains the case for the wait state of 1.
Please let me know in case you have any further queries related to this.
Thanks,
Harshit